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Crypto chips
Embeddable cryptographic processors

Below is a non-exhaustive overview of cryptographic processors, also known as crypto chips. Some chips contain a single encryption algorithm and were developed for a specific application or device, whilst others are more universal and may by found various cryptographic products.

Crypto chips on this website
Advanced Infosec machine (Motorola)
AIM
Advanced INFOSEC machine II
RAILMAN embeddable cryptographic processor with SAVILLE
CYPRIS embeddable cryptographic processor with SAVILLE
Harris SIERRA cryptographic engine
Harris SIERRA II cryptographic engine
Harris CITADEL cryptographic engine
Harris CITADEL II cryptographic engine
Philips family of cryptographic engines
Clipper Chip (used for key escrow)
 
Sorted by year
NameYearManufacturerNSA
Type		Description / examples
OQ4406 1 1974 Philips - Aroflex I, NATO
OQ4407 1 1974 Philips - T-1000 CA (Beroflex)
OQ4430 1984 Philips 1 SAVILLE, Spendex 40, Spendex 50
U-AJU 1987 Motorola 1, 2 STU-III, SECTEL 2500
OQ4434 1989 Philips - Proprietary, PNVX, etc.
OQ4435 1989 Philips - Proprietary, PNVX, RNG, etc.
OQ4436 1989 Philips - Aroflex I/II, NATO, PNVX, etc.
Fascinator 1989 Motorola 1 SAVILLE
RAILMAN 1991 NSA 1 U-AXM, SAVILLE
CYPRIS 1992 Lockheed Martin 1 Fully programmable, legacy, new
PPC100 1992 Pijnenburg - DES
PPC200 1992 Pijnenburg - RSA
GCD 1993 Philips - RNG, DES, RSA, Proprietary, etc.
Clipper 1993 NSA, Mykotronx 2 Skipjack, key escrow
PPC201 1994 Pijnenburg - RSA 1024
PPC2010 1994 Pijnenburg - 3DES, RSA, MD5
Indictor 1994 NSA, Motorola 1, 2 SAVILLE, PADSTONE, CORDOBA
GCD-Φ 1996 Philips - RNG, BATON, DES, AES, IDEA, SHA, etc.
Citadel I 1997 Harris 4 MK-128. 2
PPC101 1997 Pijnenburg - 3DES
AIM 1998 Motorola 1, 3 SAVILLE, BATON, DES, 3DES, AES, etc.
Sierra 1998 Harris 1 SAVILLE, BATON, WALBURN, etc.
GCD-Φ 2000 1999 Philips - Improved version of GCD-Φ
PPC2020 2001 Pijnenburg - 3DES, RSA, MD5, embedded ARM
Citadel II 2004 Harris 4 MK-256. 2
Sierra II 2004 Harris 1, 3, 4 SAVILLE, BATON, WALBURN, AES, etc.
SafeXcel 2004 SafeNet, Rambus - DES, 3DES, AES, ARC4, MD5, SHA, RNG
AIM II 2011 General Dynamics 1, 3 Same as AIM + ECC, ECDSA, ACME, etc.
  1. This is not a single-chip design. Multiple chips are needed to impmement the algorith,
  2. Approved for export from the USA.
Chips by designator
IDOrder no.NameManufacturerNSA
Type		Example
U-AJUON408219-2?Motorola1, 2STU-III, SECTEL 2500
U-AXM ON452600-2 RAILMAN NSA 1 KY-99
U-BI ON493700-2 CYPRIS Lockheed Martin 1 Prototype
U-KVDON637465??1KIV-7
U-SAM 1ON230295?RCA1KY-68
  1. This is not a single-chip design. Multiple chips are needed to impmement the algorith,
Literature
  1. Survey of commercially available cryptographic chips
    and IP cores implementing cryptographic algorithms
    P. Arora, M. Dugan, P. Gogte, GMU. December 2005.
Further information
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© Crypto Museum. Created: Sunday 12 May 2024. Last changed: Wednesday, 15 May 2024 - 07:38 CET.
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